Alif Semiconductor /AE302F80F55D5AE_CM55_HE_View /OSPI0 /OSPI_SPI_CTRLR1

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Interpret as OSPI_SPI_CTRLR1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0NDF

Description

OSPI Control Register 1

Fields

NDF

Number of Data Frames. When OSPI_CTRLR0[TMOD] = 0x2 or 0x3, this bit field sets the number of data frames to be continuously received by the OSPI. The OSPI continues to receive serial data until the number of data frames received is equal to this register value plus 1, which enables to receive up to 64KB of data in a continuous transfer. When OSPI_CTRLR0[TMOD] = 0x1, this bit field sets the number of data frames to be continuously transmitted by OSPI. If the Transmit FIFO goes empty in-between, OSPI masks the serial clock (OSPI_SCLK) and waits for rest of the data until the programmed amount of frames are transferred successfully.

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